This invention relates to an improvement in fault responsive protective devices, which employ timing capacitors to generate a time current characteristic inversely proportioned to fault magnitude, wherein the certainty of appropriate coordination among a number of fault responsive protective devices in a distribution system is improved. More particularly, the improvement relates to controlling the timing capacitor with a master timing capacitor when coordination among a series of fault responsive protective devices is jeopardized by faults of such a large magnitude that their individual time current characteristics tend to merge.
Generally in an electric power distribution system there are a great number of protective devices for interrupting excessive current flows which tend to damage the current conductors or other distribution equipment. It is most desirable to interrupt a fault, excessive current, with the protective device which is closest to the malfunction causing the fault in order to minimize the area of power outage. To this end a number of protective devices may be placed in series, so as to carry the same current. Then when a fault occurs, only the one closest to the fault should operate to interrupt the fault.
It is also desirable that a protective device respond quicker to faults of greater magnitude than to faults of lesser magnitude. However it is not desirable that a protective device respond quickly to every current in excess of design limits, since such currents may often be caused by a malfunction of such short duration that no harm to the system will occur. A branch a striking a power line due to a gust of wind can cause such a malfunction. Therefore, most protective devices therefore have time current characteristics which delay their response to less excessive current and yet accelerate their response, so that they respond more quickly, to faults of greater magnitude.
A graph of the time current characteristic, showing the time it takes for the device to respond to a fault of a specific magnitude, often results in a straight line when plotted on a log-log scale. Some care should be taken to coordinate among protective devices in a system so that the time current characteristic of an upstream protective device is always greater, i.e. responds more slowly, than a downstream device. Unless care is taken, a larger area than necessary will suffer power outages needlessly. Unfortunately at high magnitudes of fault the time current characteristics of many protective devices tend to merge. At these levels of fault, coordination among protective devices can be lost. When coordination is lost, several protective devices may respond, or an upstream protective device, i.e. closer to the power source, may respond before a downstream device. To ensure that coordination is not lost under these circumstances, a minimum time delay may be introduced for each of the devices, so that despite merger of their time current characteristics, the device furthest upstream will be the last to open because it has the longest minimum time delay.
A further complication can occur because all protective devices have finite design limits. If design limits are exceeded, and the protective device attempts to interrupt a fault, it may be destroyed.
An example of a protective device employed in a power distribution system is provided by U.S. Pat. No. 4,027,203 issued to myself and William N. Le Court. The device, described fully in the patent, generates its time current characteristic by employing a timing capacitor. Once excessive current is detected in the protected conductor, the timing capacitor is charged with a current which is proportional to the current in the conductor. After charging of the timing capacitor begins, or pick-up occurs, the proportional charging current continues to charge the timing capacitor as long as excessive current is flowing. At a preselected level of voltage on the timing capacitor, an output stage is activated to interrupt the current in the protected conductor. A modification of the device as illustrated in FIG. 2 of U.S. Pat. No. 4,027,203, provides a minimum time delay by clamping the inputs to the device. The inputs are proportional to currents in the conductors being protected. This clamping, achieved by a Zener diode, introduces a nonlinearity into the current used to generate the time current characteristic, and if several time current characteristics are generated by using several timing circuits all are affected, but do not achieve the same minimum time delay for each time current characteristic. Under some conditions, because of the comparatively high currents in the rectified output of the current transformers, failure of the Zener diode due to excessive power dissipation may occur. A time delay achieved with Zener diode clamping cannot be conveniently altered.